Feature |
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Internal Double-data-rate architecture with
2 accesses per clock cycle |
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VDD/VDDQ = 2.5V +/- for
(-75and -6) |
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VDD/VDDQ = 2.5V +/- for (-5) |
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Burst length of 2,4,8 |
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2.5V SSTL-2 compatible I/O |
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2,2.5,3 clock read latency |
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Bi-directional, intermittent data strobe(DQS) |
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All inputs except data and DM are sampled
at the positive edge of the system clock |
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Data Mask (DM) for write data. |
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Auto & self refresh supported |
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4K Refresh cycle / 64ms |
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Sequential & Interleaved burst
type available |
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Auto Precharge option for each burst-accesses |
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DQS edge-aligned with data for read cycles |
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DQS center-aligned with data for write cycles |
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DLL aligns DQ & DQS transitions with CLK's |
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Auto refresh and self refresh |
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4,096 refresh cycles / 64ms |