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Click to download datasheet regarding. Please note that the content of datasheet is subject to change without notice.


 　
  The EM42AM3284LBA is a high speed synchronous RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as4 meg words x 4 Banks by 32bits.  The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I /O pins. Available packages:TFBGA-90B(13mmx11mm)             

 
Feature
Internal Double-data-rate architecture with 2 accesses per clock cycle
1.8V+/-0.1V VDD/VDDQ
  1.8V LV-COMS compatible I/O
  Burst length(B/L) of 2, 4, 8, 16
  3 clock read latency
Bi-directional, intermittent data strobe(DQS)
All inputs except data and DM are sampled at the positive edge of the system clock
  Sequestial & interleaved burst type available
Auto Precharge option for each burst-accesses
DQS edge-aligned with data for Read cycles
DQS center-aligned with data for Write cycles
No DLL; CK to DQS is not synchronized
Deep power down mode
Partial Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh (TCSR) by built-in temperature sensor
  Auto refresh and self refresh
8,192 refresh cycles /64ms
DataSheet
Timing
 
　
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