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Click to download datasheet regarding. Please note that the content of datasheet is subject to change without notice.


 
 

The EM42AM3284LBB is a Double Data Rate Synchronous DRAM fabricated with ultra-high performance CMOS process containing 536,870,912 bits which organized as 4Meg words x 4 banks by 32 bits. The 512Mb DDR SDRAM uses double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I/O pins. Available packages: TFBGA-90B (13mmx8mm).

 
Feature
Internal Double-data-rate architecture with 2 accesses per clock cycle

JEDEC standard 1.8V ±0.1V VDD/VDDQ

1.8V LV-COMS compatible I/O

  Burst length of 2,4,8 or 16

3 Clock read latency

Bi-directional, intermittent data strobe (DQS)
All inputs except data and DM are sampled at the positive edge of the system clock
Data Mask (DM) for write data.

Sequential & Interleaved Burst type available

Auto Precharge option for each burst accesses

DQS edge-aligned with data for Read cycles

DQS center-aligned with data for Write cycles

No DLL; CK to DQS is not synchronized

Deep power down mode

Partial Array Self-Refresh (PASR)

Auto Temperature Compensated Self-Refresh (TCSR) by built-in temperature sensor

 

Auto Refresh and Self Refresh

8,192 Refresh Cycles / 64ms

DataSheet
Timing
 
 
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