| Feature |
|
 |
Internal Double-data-rate architecture with
2 accesses per clock cycle |
|
 |
1.8V+/-0.1V VDD/VDDQ |
|
 |
1.8V LV-COMS compatible I/O. |
| |
 |
Burst length of 2,4,8,16 |
| |
 |
Data Mask (DM) for write data |
| |
 |
3 clock read latency(CL3) |
|
 |
All inputs except data and DM are sampled
at the positive edge of the system clock |
| |
 |
Bi-directional,intermittent data
strobe(DQS) |
|
 |
Data Mask (DM) for write data |
|
 |
Sequential & Interleaved Burst type
available |
|
 |
Auto Precharge option for each burst-accesses |
|
 |
DQS edge-aligned with data for read cycles |
|
 |
Sequential & Interleaved Burst type
available |
|
 |
DQS center-aligned with data for write cycles |
|
 |
No DLL;CK to DQS is not synchronized |
|
 |
Deep power down mode. |
|
 |
Partial Array Self-Refresh(PASR) |
|
 |
Auto Temperature Compensated Self-Refresh(TCSR)by
built-in temperature sensor |
|
 |
8,192 refresh cycles/64ms |