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Click to download datasheet regarding. Please note that the content of datasheet is subject to change without notice.


 　
  The EM42BM1684RTA is a high speed synchronous RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8meg words x  4 Banks x 16 bits. The 512 Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path intemally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at I/O pins.
Available packages:TSOPII 66P (400mil)
 
Feature
Internal Double-data-rate architecture with 2 accesses per clock cycle
Single 2.5V +/- 0.2V power supply.
  2.5V SSTL-2 compatible I/O
Burst length of 2,4,8
2,2.5,3 clock read latency
Bi-directional, intermittent data strobe(DQS)
All inputs except data and DM are sampled at the positive edge of the system clock
Data Mask (DM) for write data
Sequential & Interleaved Burst type available
Auto Precharge option for each burst-accesses
DQS edge-aligned with data for read cycles
DQS center-aligned with data for write cycles
DLL aligns DQ & DQS transitions with CLK transition
Auto refresh and self refresh
8,192 refresh refresh
DataSheet
Timing
 
　
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