Feature |
|
|
Fully synchronous to positive clock edge |
|
|
Single 3.3V +/- 0.3V power supply |
|
|
LVTTL compatible with multiplexed address |
|
|
Programmable Burst Length (B/ L ) - 1,2,4,8
or full page |
|
|
Programmable CAS Latency (C/ L ) - 2 or
3 |
|
|
Data Mask ( DQM ) for Read/Write masking |
|
|
Programmable wrap sequential |
- Sequential (B/L = 1/2/4/8/full page
) |
|
- Interleave (B/L = 1/2/4/8 ) |
|
|
|
Burst read with single-bit write operation |
|
|
All inputs are sampled at the positive rising
edge of the system clock |
|
|
Auto refresh and self refresh |
|
|
4,096 refresh cycles / 64ms(15.625us) |