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The EM484M3244LBB is Mobile Synchronous Dynamic Random Access Memory (Mobile SDRAM) organized as 1Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb Mobile SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V ultra low power memory system. It also provides auto refresh with deep power saving / down mode. The data paths are internally pipelined to achieve very high bandwidth. All inputs and outputs voltage levels are compatible with LVCMOS. Available packages: TFBGA-90B (13mmx8mm).
 
Feature
Fully synchronous to positive clock edge

JEDEC Standard 1.8V Power Supply

LVCMOS Compatible with Multiplexed Address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 2 or 3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
　 - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
All inputs are sampled at the rising edge of the system clock

Support Deep Power Down Mode
 

Partial Array Self Refresh (PASR)

Auto Temperature Compensated Self Refresh (Auto TCSR)
 

Driver Strength (DS)
 

Auto Refresh and Self Refresh

4,096 Refresh Cycles / 64ms (15.625us)
DataSheet
Timing
 
　
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