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Click to download datasheet regarding. Please note that the content of datasheet is subject to change without notice.


 　
  The EM488M1644LBB, is  Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.
Available packages:TFBGA-54B(8mmx8mm)
 
Feature
Fully synchronous to positive clock edge
Single1.8V+/-0.1V power supply
LVCMOS compatible with multiplexed address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 1,2,3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
　 - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
Deep power down mode.
Auto refresh and self refresh
  Special function support.
      -PASR(Partial Array Self Refresh)
      -Auto TCSR(Temperature Compensated Self Refresh)
  Programmable drvier strength control
      -Full strength or 1/2, 1/4 of full strength
4,096 refresh cycles / 64ms(15.625us)
DataSheet
Timing
 
 
　
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