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  The EM48AM1684LBA, is Mobile Synchronous Dynamic Random Access Memory (Mobile-SDRAM) organized as 4Meg words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.                                                                     Available packages:P-VFBGA 54B (12mmx8mmx1mm)
 
Feature
Fully synchronous to positive clock edge
VDO/VDDQ= 1.8V +/- 0.15V power supply
LVCMOS compatible with multiplexed address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 2,3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
　 - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
All inputs are sampled at the rising edge of the system clock
  Auto refresh and self refresh
8,192 refresh cycles / 64ms(7.8us)
DataSheet
Timing
 
 
　
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