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  The EM48BM1684LBB  is  Synchronous Dynamic Random Access Memory (SDRAM) organized as 8Meg words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 512Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.

Available packages:FBGA 54B(8.0mmx10mm)
 
Feature
Fully synchronous to positive clock edge

VDD= 1.7V ~ 1.95V for 133MHz & 166MHz Power Supply
LVCMOS compatible with multiplexed address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 2,3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
　 - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
All inputs are sampled at the rising edge of the system clock
  Auto refresh and self  refresh.
  Partial Array Self Refresh (PASR)
8,192 refresh cycles / 64ms(7.8us)
Auto temperature compensated self-refresh(TCSR) by built-in temperature sensor
Driver strength:normal/weak
DataSheet
Timing
 
 
　
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