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The EM48AM3284LBA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 4Meg x 4 banks x 32 bits.All inputs and outputs are synchronized with the positive edge of the clock. The 512Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 1.8V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVCMOS.
Available packages: TFBGA-90B(10mmx13mm).


 
Feature
Fully synchronous to positive clock edge
Single 1.8V +/- 0.1V power supply
LVCMOS compatible with multiplexed address
Programmable Burst Length (B/L) - 1,2,4,8 or full page
Programmable CAS Latency (C/L) - 2 or 3
Data Mask (DQM) for Read / Write masking
Programmable wrap sequence - Sequential (B/L = 1/2/4/8/full page )
  - Interleave (B/L = 1/2/4/8 )
Burst read with single-bit write operation
 

Programmable Driver StrengthControl

-Full Strength or 1/2, 1/4 of Full Strength
 

Special Function Support.

-PASR (Partial Array Self Refresh)

      -Auto TCSR (Temperature Compensated Self Refresh)
 

Deep Power Down Mode.

Auto refresh and self refresh
  8,192 refresh cycles / 64ms (7.8us)
  Partial Array Self Refresh (PASR)
DataSheet
Timing
 
 
 
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